Your BTech projectcan be your own chip
Instead of another slide deck, software clone, or simulation — imagine your degree project taped out as real silicon you can hold in your hand.
Students are already doing this.
Across universities worldwide, undergraduate and graduate engineering students participate in chip design and tape-out programs as part of their academic coursework.
MIT
Massachusetts Institute of Technology
“Students in semiconductor courses can design circuits and experience the tape-out process.”
UC BERKELEY
University of California, Berkeley
“Students have taken chip designs from coursework through tape-out and fabrication.”
GEORGIA TECH
Georgia Institute of Technology
“Undergraduate students have participated in a VLSI 'Theory to Tapeout' course.”
STANFORD
Stanford University
“Hands-on VLSI coursework can take students through IC design and tapeout.”
* Verified academic programs cited as real-world examples of university-level chip design coursework. No institutional partnership or affiliation is implied. Click any case to view the official university publication.
Why not here?
Students shouldn't have to wait until they enter the semiconductor industry to experience chip design.
We believe students in India should have the opportunity to design real hardware and work toward fabrication during their degree.
From ordinary sand to extraordinary intelligence.
Chip design is the journey of turning raw geology into the most complex artifact manufactured in human history.
IT STARTS WITH SAND.
Silicon dioxide in its most humble, natural state — raw mineral quartz resting beneath our feet.
From something beneath your feet to something capable of billions of operations.
That's chip design.
This is what you could learn to create.
Your B.Tech project can be your own chip.
See what you could buildWhat could your project become?
A B.Tech or M.Tech project doesn't have to end as a simulation or slide deck. Slide through real, tangible projects engineering students can design and work toward fabricating:
Have another hardware or architecture idea in mind?
Whether you're building custom accelerators, microprocessors, or control logic, any synthesizable design can be hardened into real silicon.
Pick your route to silicon.
Start free with open first-principles foundations, or join our flagship 1-year degree project cohort to take your capstone design from concept to tape-out ready silicon.
Foundations
15 Interactive Stages • Free Forever
A question-driven path from continuous electrical voltages to synthesizable Verilog. Zero prerequisites, completely browser-based, and open to all students.
- 15 interactive pedagogical stages
- Live in-browser logic simulations
- Open to all engineering streams
Degree Project Cohort
1-Year Major Project Guidance • RTL to GDSII
Take your B.Tech / M.Tech capstone project through architecture, simulation, floorplanning, CTS, and sign-off — creating a real design for Sky130, GF180, or SCL.
Universities
Departmental Tape-Out Integration
Empower your department with cloud-based silicon workflows. Partner with Chip Factory to enable batch tape-outs and faculty-guided capstones on your campus.
- Shared multi-project shuttle reticles
- Faculty co-mentoring & curriculum mapping
- Zero software license friction
Everything included in the 1-Year Cohort
Monthly Industry Mentor Call
Dedicated monthly 1-on-1 reviews with seasoned semiconductor engineers who critique your microarchitecture, simulation, and physical design.
The Ultimate UG Resume Flex
99% of engineering resumes list software clones or simulation slides. Holding a real, fabricated silicon chip with your name on the die is an unmatched flex for top VLSI placements and global MS/PhD applications.
Algorithms, Open Source & GSoC
Learn how algorithms help in designing chips carrying billions of transistors working in sync. Master the open-source EDA flow, contribute to open-source silicon, and prepare to participate in GSoC.
Tape-Out Ready Physical Sign-Off
Generate verified GDSII files meeting foundry DRC/LVS design rules ready for manufacture on Sky130, GF180, SCL, or shared shuttles.
Tuition: ₹1,29,999 (all inclusive) • Complete 1-year guidance until major project completion.
Cloud web-based solution (no workstation or Linux needed). Scholarships up to 90% available through the screening test. Register before Dec 1, 2026 for early bird discount.
* Tuition covers all curriculum, mentor hours, EDA cloud runners, and physical design sign-off verification. Physical foundry fabrication (manufacturing the silicon wafer) is optional and depends on die area (mm²) and complexity. Read our FAQ below for transparent foundry shuttle pricing.
Frequently asked questions.
Everything you need to know about the 1-year cohort, prerequisites, pricing, scholarships, and physical foundry fabrication.
Have a specific question about your project?
Reach out directly via email to our team or chat with us on WhatsApp.
Make your project
a real chip.
Applications for upcoming degree project cohorts are open. Bring your hardware idea — and work toward fabricating silicon you designed yourself.
Cohort 01 starts Jan 1, 2027 • Early bird before Dec 1, 2026 • Scholarships up to 90%