CHIP FACTORY SILICON STUDIO
Turn Your Code Into Synthesizable Silicon.
The Build Workspace is where students write RTL, run automated OpenROAD physical design flows in WSL, and generate tape-out ready GDSII files.
Pedagogical Process Journey
Experience physical design through a smooth Left-to-Right transformation from Verilog RTL to Floorplan to 5-Metal GDSII.
Interactive Stage Ingredients
Directly dial OpenROAD and Yosys parameters (utilization, aspect ratios, CTS skews) and see live physics trade-offs.
Under-The-Hood Inspection
Step-by-step makefile recipes, exact OpenROAD TCL script calls, and real-time WNS/TNS timing slack metrics.