Now build something that is yours.
“Can you take an idea all the way from a problem statement to a physical chip?”
Sections 0–13 were a guided exploration of how semiconductors are conceived, modeled, synthesized, routed, verified, and fabricated. Section 14 is the beginning of your own journey.
The question is no longer “What is a chip?” It is: “What should YOUR chip do?”
Start with a problem, not an RTL file
Standing before an empty text editor with the desire to “write some Verilog” is a terrible way to begin a chip. Great integrated circuits start by asking: Who needs this? What problem are we solving? Why does dedicated hardware make sense over a software microcontroller? (Slide 2).
Your first chip does not need to be a 64-bit multi-core CPU or an enormous GPU. A small, completely mastered design—such as a 4-way traffic light controller, a digital security lock, an 8-bit PWM generator, or a UART communications core—gives you 100% end-to-end mastery from idea to silicon.
Interactive Project Selection & Specification Workbench (14.1 & 14.2)
4-Way Traffic Light Controller
Autonomous traffic intersection with sensor triggers and emergency override
Orchestrate safe, deadlock-free traffic flow at a busy 4-way intersection with vehicle presence sensors and emergency vehicle priority.
Requires guaranteed microsecond deterministic response and hardware-level safety locks that cannot hang or crash.
What exactly should the chip do, and what hardware is needed?
Before typing code, you freeze the System Specification: the exact input pins, output buses, operating voltage, active clock edges, reset behavior, and corner cases (Slide 3).
Then you perform Architectural Block Decomposition (Slide 4 & 5). You partition the design into:
- Sequential Memory: Flip-flop state registers and counter buffers.
- Computation Datapaths: Adders, ALUs, magnitude comparators, and shifters.
- Control Logic FSM: A Moore or Mealy Finite State Machine that orchestrates internal bus handshakes.
Architectural Block Decomposition & FSM Canvas (14.3, 14.4, 14.5)
Synchronizer & Pads
Finite State Machine (MOORE)
4-Bit Datapath ALU
Accumulator Register
Output Dependence: Outputs depend solely on the current state register bits.
Operational Impact: Offers completely glitch-free, synchronous output generation for predictable, robust ASIC control logic.
Output Dependence: Outputs depend on both the current state register AND immediate input signals.
Operational Impact: Allows 0-cycle immediate reaction times, but introduces risk of asynchronous combinational logic glitches and long timing paths.
Describe the hardware and prove that it works
RTL is a direct textual representation of physical hardware. When you write assign y = a & b;, you are creating physical PMOS and NMOS transistor networks on silicon (Slide 7).
Writing RTL is only the starting point. Hardware engineering is dominated by The Engineering Debug Loop (Slide 8 & 9): Write → Simulate → Fail → Debug → Fix → Re-Simulate. You write automated self-checking testbenches that verify reset conditions, normal traffic, and edge-case boundary scenarios.
RTL-to-Hardware Mapping & Verification Debug Loop (14.6, 14.7, 14.8)
assign y = a & b; instantiates a CMOS 2-input AND standard cell (`sky130_fd_sc_hd__and2_1`).
Metal Layers: M1 routing for A, B inputs and Y output.
| Cycle # | clk | rst_n | enable | Expected Q | Actual Simulated Q | Assertion Match |
|---|---|---|---|---|---|---|
| Cycle 0 | 0 | 0 | 0 | 0 | 0 | PASS |
| Cycle 1 | 1 | 1 | 1 | 1 | 1 | PASS |
| Cycle 2 | 0 | 1 | 1 | 2 | 2 | PASS |
| Cycle 3 | 1 | 1 | 1 | 3 | 0 | MISMATCH (Bug in RTL) |
| Cycle 4 | 0 | 1 | 1 | 4 | 1 | MISMATCH (Bug in RTL) |
| Cycle 5 | 1 | 1 | 0 | 4 | 1 | MISMATCH (Bug in RTL) |
Is our hardware practical?
A design that passes simulation is functionally correct, but is it viable on silicon? (Slide 10).
You run Logic Synthesis in Yosys against the SkyWater 130nm standard cell library (`sky130_fd_sc_hd`), mapping abstract behavioral equations to physical gates and measuring the PPA triad: Power (mW), Performance / Timing (F_max in MHz), and Silicon Die Area (μm²).
Logic Synthesis & PPA Optimization Dashboard (14.9 • Slide 10)
Can our design become a physical chip?
In the physical realm, your gate netlist enters OpenROAD (Slide 11 & 12). You construct the die floorplan and power grid, place millions of transistors into legalized standard cell rows, synthesize a balanced H-tree clock network (CTS) to kill clock skew, and pathfind multi-layer copper routing tracks (M1–M4).
Finally comes Signoff (Slide 13): checking Static Timing Analysis (STA), Design Rule Checking (DRC), and Layout Versus Schematic (LVS). Once certified, you export the golden GDSII stream database and transmit your chip to the foundry!
OpenROAD Physical Design & Signoff Engine (14.10, 14.11, 14.12)
Exhaustive STA timing closure, geometric DRC rules, and LVS schematic matching.
The 10-Milestone Project Pipeline: From Idea to GDS (14.1 to 14.12)
Formal statement of user need, target application, and hardware justification.
# PROJECT PROBLEM DEFINITION Problem: 4-way traffic intersection controller with vehicle detection and emergency priority. Motivation: Microsecond deterministic response and hardware-level safety isolation. Target Foundry: SkyWater 130nm Open PDK (sky130_fd_sc_hd).