How do we design a complete digital machine?
“We have computation. We have memory. We have control. How do these individual circuits come together to form an entire functioning digital system?”
In our journey through digital electronics, we have mastered individual primitives: logic gates in Section 2, arithmetic ALUs in Section 3, registers in Section 4, and finite state machines in Section 5. A single logic gate is like a single brick, but our goal is to build an entire automated city. In this section, we transition from drawing basic circuits to systems-level architecture—combining computation, storage, and control into complete, real-world machines.
What does a digital machine actually need?
Every complete digital system—whether it is a simple digital stopwatch, a microwave timer, or a 64-bit supercomputing processor—requires exactly five fundamental components to function correctly:
- Inputs: What information enters the system from the outside world (push-buttons, sensors, serial streams)?
- Outputs: What final result or action does the system produce (7-segment displays, LEDs, motor actuators)?
- Memory: What specific data, counts, or operational states must be remembered across clock cycles?
- Calculation: What mathematical or logical operations must be computed (ALUs, adders, comparators)?
- Control: What mechanism orchestrates the timing, state changes, and enable signals for all moving parts?
The 5 Pillars of Any Digital System Architecture
Inputs — “What information is entering the system?”
Captures external stimuli or incoming data streams and converts them into digital logic voltage levels (HIGH/LOW).
Key Architectural Rule: No single gate operates in isolation. Every complete digital machine—from a microwave controller to a RISC-V processor—is composed of these exact five pillars working in lockstep synchronization.
Where does the computation happen?
In Section 3, we built adders, comparators, and multiplexers. In a complete digital system, these combinational circuits are grouped into a dedicated physical highway called the Datapath. The computation centerpiece of the datapath is the Arithmetic Logic Unit (ALU).
To feed numbers into the ALU, blocks must communicate. A single electrical wire carries only a single bit (a Signal). But transmitting an 8-bit or 16-bit number one bit at a time over a single wire is slow. By bundling parallel wires together into a Bus, an entire numerical word travels simultaneously in a single clock transition.
Where Computation Happens: The Datapath & Multi-Bit Buses
In a digital system, the Datapath is the physical highway of registers, multiplexers, and arithmetic circuits where data is routed and transformed. The core computation heart is the Arithmetic Logic Unit (ALU).
Where does the information live?
There is a critical distinction at the heart of computer architecture:
“What should the value become?”
Combinational logic gates instantly transform inputs into outputs, but have zero retention. When inputs change, previous outputs vanish.
“Where do we keep the value?”
Flip-flop registers act as the warehouse, capturing data on clock edges ($\uparrow$) and holding values rock-solid across cycles.
By combining register banks (Accumulators, Operand Registers, Program Counters) with the ALU, the machine can hold onto intermediate calculations, accumulate totals, and feed past results back into future calculations.
Where Information Lives: Synchronous Multi-Bit Registers
While the ALU calculates values instantaneously, combinational logic cannot hold onto them. The moment inputs change, previous outputs vanish. Registers (Digital Memory) act as the warehouse of the machine—capturing data on clock edges ($\uparrow$) and holding it rock-solid for future operations.
Who decides what happens next?
We have computation (the ALU) and storage (Registers). But who decides which operation the ALU should compute? Who tells Register A to open and Register B to latch? Who decides when the calculation is finished?
This is the role of the Control Unit. The Control Unit is a Finite State Machine (FSM) that acts as the brain and central nervous system of the digital machine. At each clock cycle, the FSM transitions through operational states and issues precise 1-bit and multi-bit Control Signals:
MUX_SEL— Selects which bus feeds into the arithmetic block.ALU_OP— Instructs the ALU to Add, Subtract, or Compare.REG_EN— Write enable strobe dictating which register captures data.STATUS_FLAGS— Feedback from the datapath (Zero flag, Carry, Comparison) informing the FSM of calculation outcomes.
Datapath (The Body) vs. Control Unit (The Brain)
A complete digital machine is split into two complementary planes: the Datapath (which manipulates numerical words) and the Control Unit (which decides what the datapath should do and when).
How do all these pieces work together?
When Inputs, Memory, Calculation, and Control are wired together on silicon, they form a complete, autonomous digital system. In Slides 11, 12, and 13, the curriculum demonstrates this synergy through classic real-world machines:
100 Hz Oscillator + Start/Stop FSM + Cascading BCD Counters + 7-Segment Decoders.
Keypad Input + Secret Code Register + 4-Word Equality Comparator + Lock FSM.
Accumulator Register + Instruction Opcode + ALU Core + Sequential Execution.
Complete Digital Machines in Action: Inputs, Memory, ALU & FSM
Slide 11: A precision timekeeping system integrates all 5 pillars: Inputs (Start/Stop, Reset), Control Unit FSM (Counting / Paused), a 100 Hz Clock Oscillator, cascading BCD Counters & Memory Latches (1/100s, Seconds, Minutes), and BCD-to-7-Segment Display Decoders driving the LED panels.
100 Hz Master Oscillator + Start/Stop debounce flip-flops.
Enables or gates the 100Hz clock pulse into the counters.
BCD 1/100s rolls over at 99 → Sec counter rolls over at 59 → Min counter.
Translates 4-bit BCD binary words into 7 active LED segment lines.
Can we describe the whole machine before building it?
Designing a complex digital machine as a single giant monolithic circuit leads to wiring tangles, impossible debugging, and complete project failure. Modern chip design relies on Modular Architecture:
Breaks down massive systems into self-contained blocks (ALUs, decoders, UART controllers) allowing parallel engineering teams.
Isolates errors within module boundaries, allowing exhaustive unit testing before full chip integration.
Proven silicon IP blocks can be reused across dozens of chip generations without redesigning from scratch.
Clean module boundaries require strict Interface Contracts and Handshake Protocols (such as VALID and READY), alongside rigorous planning for Corner Cases and deterministic System Reset Conditions.
Pre-Hardware Specification, Clean Boundaries & Scaling
Slide 8: Dividing large circuits into modular blocks requires strict boundaries. Modules use Handshake Protocols (such as VALID and READY) to guarantee reliable data transfer without data loss or buffer overruns.