Our circuits can calculate, but can they remember?
“How can a physical circuit of semiconductor switches hold onto a piece of information after the input is gone?”
In Section 3, we assembled adders, multiplexers, and an entire ALU. But all of those circuits share a critical limitation: they are purely combinational. The moment an input wire changes, the previous calculation disappears forever. In this section, we will cross one of the most profound boundaries in computer engineering: discovering how feedback loops, clock pulses, flip-flops, and registers allow circuits to carry information through time.
What does “remember” mean for a circuit?
To understand how a circuit remembers, we must first examine why standard logic gates do not. Consider a basic AND gate: does it remember its previous input? The answer is definitively no.
Why are combinational circuits “memoryless pass-through calculators”?
An AND gate or Adder has instantaneous dependency. Its output depends strictly on whatever electrical signals are present at its input terminals right at this exact microsecond. The instant the inputs change, the previous output value is permanently lost.
How can we make an output depend on the past?
By introducing a feedback loop into the circuit design! By taking the output wire from a logic gate and routing it back into one of its own input terminals, we force the circuit to continuously feed its current state back to itself, trapping electricity in a self-reinforcing ring.
4.1 Combinational Logic vs Memory: The Power of Feedback
Combinational logic circuits are instantaneous pass-through calculators: the moment inputs change, the previous output is lost forever. Introducing a feedback loop allows a circuit to trap electricity and hold state.
An AND gate calculates strictly based on whatever electrical signals exist at its terminals right at this microsecond.
The Limitation: As soon as Input A or B drops to 0, Output Y immediately drops to 0. It cannot remember that it was previously 1!
By routing the output wire back into the input, the circuit continuously feeds its own state back to itself.
Bistable Memory: Once pulsed, the state Q = 0 is sustained forever by the continuous feedback current, even when your pulse input is completely gone!
Can a circuit remember one bit?
When a circuit successfully feeds its own output back into its input, it begins to exhibit bistable behavior: it locks itself into one of two highly stable physical states (sustained HIGH or sustained LOW).
What is an SR Latch?
An SR Latch is constructed from two cross-coupled NOR or NAND gates. It has two inputs: Set (S) to force the stored bit to 1, and Reset (R) to force the stored bit to 0. When both inputs are LOW (S=0, R=0), the latch enters HOLD MODE, holding its trapped state indefinitely without power dissipation.
What does “Level-Sensitive” and “Transparent” mean?
In a Gated D-Latch, an Enable line controls writing. While Enable is HIGH, the latch is transparent: any changes to Data D flow directly through to output Q. When Enable drops to LOW, the latch closes and locks the value. However, transparency creates a critical window of vulnerability: unwanted noise or glitches on D will corrupt the stored state while Enable is active!
4.2 Cross-Coupled Latches: Level-Sensitive 1-Bit Storage
Connecting two NOR gates in a cross-coupled feedback loop creates the fundamental SR Latch. Adding an Enable signal creates the Gated D-Latch, which becomes transparent when Enable is HIGH.
| S | R | Action | Q(next) |
|---|---|---|---|
| 0 | 0 | HOLD (Memory) | Q(prev) |
| 0 | 1 | RESET (Clear) | 0 |
| 1 | 0 | SET (Write 1) | 1 |
| 1 | 1 | INVALID (Forbidden) | Unstable |
(S=0, R=0), the latch enters HOLD MODE: it preserves its stored state without any power dissipation or active refresh.Why do we need a clock?
As digital circuits scale to millions of gates, asynchronous designs encounter a catastrophic problem: different physical wire lengths and transistor switching delays mean electrical signals arrive at staggered nanoseconds, causing glitches and race conditions.
The Master Drumbeat for the Chip
To coordinate changes and eliminate race conditions, digital systems use a global synchronization signal that acts like a conductor's baton or a master drumbeat: The Clock Signal. A clock is a continuous electrical square wave oscillating regularly between HIGH (1) and LOW (0).
What is a Clock Edge?
Within the square wave, the most critical moments are the instantaneous transitions:
• Rising (Positive) Edge (↑): Transition from LOW (0V) to HIGH (3.3V).
• Falling (Negative) Edge (↓): Transition from HIGH (3.3V) down to LOW (0V).
These sub-nanosecond transition points are used as the exact trigger events for memory elements, guaranteeing that all arithmetic logic has settled cleanly before sampling.
4.3 The Clock Signal: The Conductor's Baton of Silicon
To coordinate billions of transistors and eliminate race hazards, digital chips rely on a global periodic clock signal. Transition edges (Rising and Falling) define the exact nanosecond when data is sampled.
Across a silicon chip, wires have different lengths and transistors have varying switching speeds. Without synchronization, electrical signals arrive at staggered nanoseconds, causing temporary invalid glitches.
The clock period guarantees a generous settling window. Combinational adders and ALUs calculate freely while the clock is running; all memory registers sample the clean, stabilized results only on the rising clock edge!
What is a flip-flop?
The D Flip-Flop is the cornerstone of modern synchronous memory. Unlike a latch, a flip-flop is strictly edge-triggered: it updates its stored bit ONLY during the exact instant of a clock edge transition.
Rising Edge Sampling & Hold State
At the precise nanosecond the clock rises from LOW to HIGH (↑), the data input signal (D) is sampled and firmly locked into output Q. Between clock edges, the flip-flop completely ignores any input changes on wire D. The output Q remains frozen, holding its stored value safely.
Why does Edge-Triggering create robust timing boundaries?
Edge-triggering isolates combinational logic stages from one another. By only allowing data to pass at specific, synchronized nanoseconds, it creates clean timing boundaries. Data moves in lockstep across billions of transistors, completely eliminating the risks of glitches and race conditions that plague level-sensitive latches.
4.4 The D Flip-Flop: Edge-Triggered Synchronous Storage
The D Flip-Flop updates its stored output Q exclusively at the instantaneous rising edge (↑) of the clock signal. Between clock edges, all data fluctuations on wire D are completely ignored.
While CLK remains HIGH, any changes or glitches on Data D flow directly into Q.
The D Flip-Flop ignores all data changes between clock edges. It only samples D at the exact nanosecond of the rising edge (↑).
Can we remember multiple bits?
Now that we can reliably store one bit using a D flip-flop, how do we scale up to store words, bytes, and numbers?
The Multi-Bit Parallel Register
To store 8 bits of data, we place 8 D flip-flops side-by-side in parallel and connect them to a single shared global clock line. Because they share the exact same clock pulse, all 8 bits are sampled and saved simultaneously in lockstep. This synchronized group is called a Register.
What do registers store in a real CPU?
Registers are the fastest storage in computing:
• Binary Numbers: Storing integer operands (e.g. 00101010₂ = 42₁₀).
• Machine State Tracking: Holding hardware status flags (Zero, Carry, Negative, Overflow) and current state variables for state machine sequencing.
4.5 Multi-Bit Registers: Parallel Storage for Data & State
Connecting 8 D Flip-Flops in parallel to a shared global clock line creates an 8-bit Register. All bits sample their inputs simultaneously on every clock edge, holding binary numbers and critical machine states.
D[7:0]: the register output Q[7:0] remains rock-solid and unchanging until the exact moment you pulse the global clock line!The Journey: From Pass-Through Logic to Multi-Bit Registers
Routing output back to input traps electric charge and creates permanent state.
Level-sensitive 1-bit memory capturing values while Enable is active.
Master drumbeat isolating logic stages on instantaneous rising edges (↑).
Parallel flip-flops holding variables, status flags, and machine state.
Now our circuit can calculate and remember...
can it change its behavior over time?
We have built circuits that calculate, and registers that remember. But what happens when the next output of the circuit depends on what it remembered a moment ago?
By combining combinational logic with memory registers, we can build circuits that step through sequences, remember where they are in a process, and execute multi-step algorithms: Finite State Machines (FSMs).