How do we know the physical chip is actually going to work?
“We have routed millions of transistors and generated a complete physical layout. But a layout that looks beautiful is not necessarily a layout that will work. How do we prove it before spending millions of dollars on fabrication?”
In Section 11, you completed the physical design pipeline: floorplanning the die, legalizing standard cell rows, synthesizing an H-Tree clock network, and routing multi-layer metal tracks in OpenROAD.
Now you face the most rigorous phase in semiconductor engineering: Physical Verification & Signoff. You must mathematically prove that signals arrive on time under harsh voltage/temperature variations, that polygons obey foundry photolithography design rules, and that the drawn metal matches the post-synthesis gate netlist with 100% graph isomorphism!
How do we know the signals will arrive on time?
In synchronous digital design, flip-flops sample data at the rising edge of a clock. But real transistors take time to charge internal nodes, and real copper interconnects add resistance ($R$) and capacitance ($C$) that delay signals.
Every receiving register imposes two strict temporal sampling boundaries (Slide 4 & 5):
- Setup Time (T_setup): Data must arrive and remain stable before the clock edge arrives. If data arrives too late, the register captures old data or enters a destructive metastable state.
- Hold Time (T_hold): Data must remain stable for a minimum duration after the clock edge. A newly launched signal racing through an ultra-fast path can overwrite the receiving register before the previous cycle is latched!
12.1 Interactive Setup & Hold Timing Engine
All timing paths arrive with adequate setup window clearance before the clock edge and remain stable past the hold window requirement.
• Setup violations are frequency-dependent. If your datapath is too slow (T_data > T_clk - T_setup), you can always reduce the clock frequency to make it pass.
• Hold violations are frequency-independent. If new data arrives in < 0.25 ns, it corrupts the receiving register regardless of whether the clock period is 2.0 ns or 100 ns! Fix: Physical insertion of delay buffers into fast paths.
How do we check every timing path?
A real chip contains millions of registers and billions of potential timing paths. Running dynamic testbench simulation would take centuries and still miss corner-case timing paths (Slide 3).
Instead, engineers use Static Timing Analysis (STA). STA breaks the entire circuit into a directed graph, calculates the worst-case propagation delay along every path, and computes Slack:
STA must evaluate timing across multiple PVT (Process, Voltage, Temperature) corners (Slide 6). The Slow Corner (SS, 0.9V, 125°C) breaks setup constraints by slowing down gates, while the Fast Corner (FF, 1.3V, -40°C) accelerates gates and triggers hold violations!
12.2 Static Timing Analysis (STA) & PVT Corner Verification
What if the layout breaks a manufacturing rule?
We cannot manufacture arbitrary geometric polygons on silicon. Transistors and wires are printed using deep ultraviolet (DUV) light masks and chemical etching.
Due to optical diffraction and chemical-mechanical polishing (CMP) limits, the semiconductor foundry mandates thousands of strict geometric rules (Slide 9 & 10):
- Minimum Width: Traces drawn too narrow suffer from wire necking, breaks, or electromigration.
- Minimum Spacing: Parallel wires drawn too close bridge together during lithography, creating catastrophic short circuits.
- Metal Density & CMP: Sparse metal areas cause oxide dishing and wafer surface erosion during polishing.
- Plasma Antenna Effect: Long metal lines collect static charge during plasma etching, destroying fragile MOSFET gate oxide unless discharge diodes are inserted.
12.3 Design Rule Checking (DRC) & Manufacturing Legality
The photolithography mask generator will reject this layout. Geometry violates wafer fabrication tolerances.
Photolithography diffraction bridges adjacent copper traces, creating fatal short circuits.
The layout looks correct. But did we build the right circuit?
A layout can have zero timing violations (STA clean) and zero geometric defects (DRC clean), but still be completely non-functional if the router connected the wrong pins (Slide 11 & 12)!
Layout Versus Schematic (LVS) software mathematically reconstructs transistors and electrical nets directly from GDSII physical polygons (Parasitic Extraction) and performs graph isomorphism against the golden post-synthesis netlist.
LVS catches four fatal error classes:
- Short Circuits: Distinct logical nets (e.g. VDD and VSS) merged in layout.
- Open Wires: Broken continuous traces or missing vias leaving pins floating.
- Device Parameter Mismatches: Transistor width ($W$) or length ($L$) differing from library specs.
- Pin Connection Failures: Mislabeled or missing primary I/O boundary ports.
12.4 Layout Versus Schematic (LVS) Netlist Extraction & Verification
Extracted physical layout netlist graph is 100% isomorphic to golden synthesized gate netlist.
What happens when a check fails?
Physical design is not a single button press. When a verification check fails, engineers do not start from scratch. They execute an Engineering Change Order (ECO) (Slide 14).
The ECO loop follows four closed steps:
Only when all four checks pass (Functional Simulation, STA Timing Closure, DRC Cleanliness, and LVS Equivalence) is the design certified for Golden Tapeout Signoff (Slide 13)!
12.5 ECO Iterative Loop & Golden Tapeout Signoff Gate
Verilator & Icarus Verilog testbenches confirm zero behavioral regressions across all test vectors.
Zero negative setup slack and zero hold race violations across SS, TT, and FF operating PVT corners.
Zero width, spacing, density, notch, or antenna rule violations across all photolithographic layers.
Netlist extraction confirms complete 1-to-1 electrical graph isomorphism with zero shorts or opens.
All 4 golden signoff milestones are clean. You may officially lock the GDSII database and submit to the foundry.